1. Field of the Invention
The present invention relates to a .pi./2 phase shifter, and particularly to a .pi./2 phase shifter for use in a quaternary modulator-demodulator in digital communications.
2. Description of the Related Art
Modulation methods such as QPSK (quaternary phase shift keying) used in the field of digital communications require high-speed and highly accurate .pi./2 phase shifters for conferring a precise .pi./2 phase shift on-the carrier signal (local signal).
FIG. 1 shows a .pi./2 phase shifter of the prior art. This example of the prior art employs a T flip-flop 101 and is constructed such that carrier signal L.sub.0 is inputted to T flip-flop 101 by way of frequency multiplier 106.
A phase shifter employing a T flip-flop operates at high speed and with provided with the mutual characteristics of the transistor, readily provides signals having accurate .pi./2 phase differences of 0.degree., 90.degree., 180.degree., and 270.degree.. Such phase shifters are moreover easy to fabricate within an IC and are therefore widely used in, for example, quaternary modulation-demodulation ICs.
However, the carrier signal (L.sub.0) is 1/2-frequency divided in a phase shifter employing a T flip-flop, and frequency multiplier 106 must therefore be provided in order to double the L.sub.0 signal in advance.
FIG. 2 is an output waveform chart of frequency multiplier 106.
A double-balance mixer is generally employed as frequency multiplier 106, the output of a double-balance mixer being represented by the following formula: EQU Acosf.sub.0 .times.Bcosf.sub.0 =(Ccos2f.sub.0 +D)/2
Here, D represents DC offset, and when a large-amplitude signal is inputted as the input signal, or when the gain of frequency multiplier 106 is great, distortion occurs in the output waveform as shown in FIG. 2 due to clipping of the upper limit and lower limit of the dynamic range. When this distorted doubled wave is inputted to T flip-flop 101, any phase error diverging from 90.degree. in the output signal is magnified.
FIG. 3 illustrates a second example of the prior art. This example is provided with CR-RC phase shifter 221 to prevent the occurrence of distortion in the output of frequency multiplier 222. FIG. 3(a) is a block diagram showing the construction of this example, FIG. 3(b) shows the gain characteristics of CR-RC phase shifter 221, and FIG. 3(c) is a waveform chart of the output of frequency multiplier 222.
CR-RC phase shifter 221 is provided in the section preceding frequency multiplier 222. In this case, a combination of the constants of CR and RC results in a phase difference for each of the outputs of 90.degree., and the output of frequency multiplier 222 is therefore: EQU Acosf.sub.0 .times.Bsinf.sub.0 =(Ccos2f.sub.0)/2
The output waveform is as shown in FIG. 3(c), and therefore, the problem of increased phase error can be basically solved.
However, as shown in FIG. 3(b), each of the outputs of CR-RC circuit 221 describe symmetrical gain-frequency (f) characteristics, and consequently, the operating frequency range of this type of phase shifter is limited to the vicinity of frequencies f.sub.0 having equal gain.
FIG. 4 is a block diagram showing the construction of a third example of the prior art in which an APC (automatic phase control) circuit disclosed in Japanese Patent Laid-open No. 87822/90 is employed.
Comparison signal 402 outputted by voltage-controlled oscillator (VCO) 406 passes through phase shifter 405 and is detected at phase detector 404 with respect to reference signal 411 inputted from reference signal input terminal 401. The output voltage 409 of this phase detector 404 is smoothed by low-pass filter 407. The sensitivity of the detection of comparison signal 402 outputted by VCO 406 with respect to reference signal 411 at phase detector 403 is then controlled by detection voltage 409.
The output of the above-described phase detector 403 is smoothed by low-pass filter 408 and supplied to VCO 406, and this detection output 410 is set such that the detection sensitivity decreases when detection output 409 is high (a phase difference of 0.degree. being highest) and increases when detection output 409 is low (a phase difference of 180.degree. being lowest). In other words, an ideal APC control system can be constructed if detection gain is set to a controllable prescribed value at a phase difference of 0.degree. (360.degree.), and detection gain is controlled to a maximum at a phase difference of 180.degree..
In the .pi./2 phase shifter of the first example of the above-described prior art, a frequency multiplier is required to obtain gain of a frequency band of up to twice the frequency L.sub.0. However, such a multiplier requires a large current, and this current consumption poses a problem in the field of digital communications, which requires low power consumption, and particularly in mobile communications.
Apart from the problem of current consumption, the use of a circuit that operates on low voltage for the sake of lowering current consumption imposes a limit on the signal intensity of input signals and limits the dynamic range of the multiplier, thereby introducing distortion in the output waveform, and as a consequence, leads to inaccuracy in the 90.degree. phase difference with the output of the T flip-flop. . However, such a circuit operates over a broad band.
In the second example of the prior art, the CR and RC outputs are each: EQU A=Vin/(1+j.omega.CR) EQU B=(j.omega.CR).times.Vin/(1+j.omega.CR)
The amplitude of 2f.sub.0 in the output component becomes small when the input of the multiplier reaches 10 mV, and as a result, the T flip-flop malfunctions. The operating frequency range when set such that 1/2.pi. CR=250 MHz consequently extends from about 50 to 400 MHz, and an accurate .pi./2 phase shifter that operates over a broad band, and moreover, that does not exhibit a dependence on input signal amplitude is therefore difficult to achieve.
In a case employing the APC circuit as shown in the third example of the prior art, phase control is accomplished by directly varying the oscillation frequency of VCO 406 by the phase detection output 410 derived from output signal 402 of VCO 406 and reference signal 411 inputted from reference signal input terminal 401. As a result, variations occurring during fabrication, temperature fluctuations, or fluctuations in supply voltage occurring in VCO 406 or phase detector 403 of the circuit are manifested as phase error in detection voltage 410 as shown in FIG. 5, thereby preventing accurate phasing.